Central processing unit

Results: 2609



#Item
51SIMGREEN 101 Energize your publications with SIMGRID Power-up (or down) your application with SIMGRID Da SimGrid Team  June 11, 2015

SIMGREEN 101 Energize your publications with SIMGRID Power-up (or down) your application with SIMGRID Da SimGrid Team June 11, 2015

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Source URL: simgrid.gforge.inria.fr

Language: English - Date: 2015-06-11 05:13:43
52wgc2_OA_title.fm Page i Thursday, April 20, :25 PM  fro m WRITE GREAT CODE V ol um e 2 : T hi nk in g Low -Lev el , W r i t in g Hi gh -Lev el

wgc2_OA_title.fm Page i Thursday, April 20, :25 PM fro m WRITE GREAT CODE V ol um e 2 : T hi nk in g Low -Lev el , W r i t in g Hi gh -Lev el

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Source URL: tptp.cc

Language: English - Date: 2013-08-27 07:52:46
53ChapterIntroduction

ChapterIntroduction

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Source URL: www.warthman.com

Language: English - Date: 2003-03-07 17:54:29
54cs281: Introduction to Computer Systems  Project Lab: The Cachelab – Simulating a Cache Controler Distributed: Monday, Nov. 30, Due: Monday, Dec. 7 at midnight  Introduction

cs281: Introduction to Computer Systems Project Lab: The Cachelab – Simulating a Cache Controler Distributed: Monday, Nov. 30, Due: Monday, Dec. 7 at midnight Introduction

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Source URL: personal.denison.edu

Language: English - Date: 2015-11-30 11:25:52
55Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture

Intel Architecture Software Developer’s Manual Volume 1: Basic Architecture

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Source URL: www.cs.bu.edu

Language: English - Date: 2005-03-23 22:57:42
56Cadastre as pivotal key register in national and European eGovernement Martin Salzmann Cadastre, Land Registry and Mapping

Cadastre as pivotal key register in national and European eGovernement Martin Salzmann Cadastre, Land Registry and Mapping

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Source URL: en.foldhivatal.hu

Language: English - Date: 2011-06-14 14:16:30
57Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1  CRD/NERSC, Lawrence Berkeley National Laboratory Ber

Improving Memory Subsystem Performance using ViVA: Virtual Vector Architecture Joseph Gebis12 ,Leonid Oliker12 , John Shalf1 , Samuel Williams12 ,Katherine Yelick12 1 CRD/NERSC, Lawrence Berkeley National Laboratory Ber

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Source URL: crd.lbl.gov

Language: English - Date: 2012-09-06 23:57:27
58Monitoring Performance and Power for Application Characterization with the Cache-aware Roofline Model Diogo Ant˜ao, Lu´ıs Tani¸ca, Aleksandar Ilic, Frederico Pratas, Pedro Tom´as, and Leonel Sousa INESC-ID / Institu

Monitoring Performance and Power for Application Characterization with the Cache-aware Roofline Model Diogo Ant˜ao, Lu´ıs Tani¸ca, Aleksandar Ilic, Frederico Pratas, Pedro Tom´as, and Leonel Sousa INESC-ID / Institu

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Source URL: www.inesc-id.pt

Language: English - Date: 2015-03-03 11:08:46
59Intel SGX Explained Victor Costan and Srinivas Devadas ,  Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology

Intel SGX Explained Victor Costan and Srinivas Devadas , Computer Science and Artificial Intelligence Laboratory Massachusetts Institute of Technology

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Source URL: eprint.iacr.org

Language: English - Date: 2016-08-12 18:27:31
60cs281: Introduction to Computer Systems  CPUlab – Y86 Hardwired Control Nov

cs281: Introduction to Computer Systems CPUlab – Y86 Hardwired Control Nov

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Source URL: personal.denison.edu

Language: English - Date: 2015-11-10 08:29:13